The present invention relates to CMOS bus switching structures, especially to those operating under constraints of high speed and low power.
Background
Technological advances in digital electronics have led to circuits operating at ever increasing speeds. With the increase in speed comes a thermal restriction which drives circuit designers to use lower voltage circuits. As a result, low-voltage bus switches are required to maintain the high-speed data traffic in these systems. Low-voltage crossbar switches provide a necessary solution for maintaining reliable data traffic in these high-speed systems. However, low-voltage bus switches require stringent control of power supply sequencing to avoid the injection of disturbances onto the bus when power comes up.
Prior Art Structures
Crossbar switches have been in existence for some time and are commonly used in multiprocessor computing systems, telephone switching systems, and other complex systems. A crossbar switch is one which has a number of vertical and horizontal paths, and is controlled for the purpose of connecting any one vertical path with any one horizontal path. The concept is particularly relevant to computers where a number of buses are interconnected.
A very basic prior-art CMOS switch (as shown in FIG. 2 and discussed later in more detail) may use an N-channel pass transistor controlled by an output-enable signal OE with a supply voltage of 5 V. A problem with this implementation is that the NMOS threshold voltage V.sub.T causes a loss of headroom: if line A is at 5 V, the switch shown cannot pull line B above about 4 V (or more precisely, VCC-V.sub.TN).
One circuit which addresses this problem adds a P-channel pass transistor in parallel with the N-channel pass transistor (as shown in FIG. 3 and discussed later). An inverter is also added between the output-enable circuit and the PMOS transistor, so that both of the pass transistors turn on and off at approximately the same time. This "pass gate" configuration eliminates the headroom problem with low power supply voltages since the output can go as high as the input voltage (no saturation). However, a new problem is created when the voltage supply is powered-down. Under power down conditions, the PMOS transistor may be on (if its gate voltage leaks down to ground while its source is still above the absolute value of V.sub.TP). This means that the two buses will no longer be isolated from one another and will lead to undesirable bus disturbances.
Another drawback to the NMOS/PMOS parallel implementation occurs when there is a large positive spike on one of the bus connections. Adding the P-channel pass transistor in parallel to the NMOS device makes the circuit susceptible to input overvoltages when the device is in the blocking state. In this case, if a voltage appears on one of the bus lines which is more than one V.sub.TP above the PMOS gate voltage (which is at the power supply voltage VCC), the PMOS will begin to turn on, and the spike will propagate through. This result is very undesirable and may result in unreliable bus signals and even disable a system.
Bus-Isolation Control Circuit for a Low-Voltage Bus Switch
The present application discloses a circuit which improves reliability and predictability of circuit performance during power sequencing of low-voltage CMOS crossbar switches. A voltage reference circuit monitors the state of the power supply and provides a control signal when the supply is powered up or down. The control signal is input to blocking transistors, which can provide power to the bus switch when the supply is powered down. The control circuitry basically steals power from either I/O terminal when the supply voltage goes down. The gate of the PMOS is pulled high to keep the switch open and isolate the buses.
An advantage of this solution is that it allows for the creation of a new family of low-voltage crossbar switches which work well in reduced power supply voltage applications. Another advantage is that it is not necessary for the bus switches to be powered up before any voltage hits the bus lines. This method eliminates the need for special power-sequencing circuitry in the system design, resulting in a less complex, and therefore, less expensive system, especially for "hot swappable" cards which will be plugged in with the system power on.